Provided by www.YuvaJobs.com - 25  August  2006  ,Whole Testpaper 


Written test consists of 4 secetions
Digital--30marks
Communications---20marks
Computer---20marks
Aptitude--30marks
Each questions carry weightage differently
Digital:
It includes both STLD ,VHDL and Microprocesers.
       1)Design 3:1 multiplexer  using one tri-state buffer,AND gates and NOT gates.
       2)The no of 2-input XOR gates required to design 19-inprt XOR gate?
       3)A 26Kbyte memory,there is memory it contains 12 adderss lines and 4 bit data  bus,the number of these type of memories required to design 26Kbyte memory?
        4)Write a VHDL or Verilog HDL code for
            input:a,clock,reset
            output:out
            out is assigned to 1 when a is ,1, for two clock cycles.
        5)what is the output of following fig.100ps is the delay for XOR gate and 50ps for AND gate .all +ve and -ve edges start at boundaries of nanoseconds.(actually the output of fig is  A(B(notC)+(not B)C) ,and the waveforms are given).
        6)design forwhich the output is 10MHz clock,input to that circuit is 30MHz.
Communications:
        7)  What is shonan,s theorem?
        8)X is Gaussianly distribuyed signal
             a)p(X