Provided by www.YuvaJobs.com - Cisco Aptitude - General 


Some Sample&nbsp; questions (m.tech.)&nbsp; tech.--24, apti.--20


On cmos power( formula- P=CV*Vf

Lowest noise margin in which logic family--a) TTL&nbsp;&nbsp; b)&nbsp; CMOS&nbsp;&nbsp; c)&nbsp;&nbsp; biCMOS&nbsp;&nbsp; d)&nbsp;&nbsp;&nbsp; all have same&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;

If CMOS has tr(rise time)=tf.find Wp/Wn. given beta(n)=2*beta(p)

gm of a transistor is proportional to&nbsp;a)Ic b)Vt c)1/Vt d)none

If A and B are given in 2,s complement find A-B in decimal.

Set up time,hold time ,clock to Q delay time (very important)

.3 questions on opamp (transfer function)(2 marks each)

2 questions on sequence detector (2 marks each)

Logic function boolean expressions(true/false) (3 question-1 mark each)probabily all false

In I/O mapped how do you represent memory(1 mark)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;

The design of FSM(finite state machine) will--&nbsp;&nbsp;&nbsp;a)&nbsp; increase time of design&nbsp;&nbsp;&nbsp;b)&nbsp; increase delay&nbsp;&nbsp;&nbsp;c)&nbsp; increase power&nbsp;&nbsp;&nbsp;d)&nbsp; all of the above

K-map minimization

Phase locked loop(PLL) 1 question sachin&nbsp;
Provided by www.YuvaJobs.com - Cisco Aptitude - General