Bachelors degree in Engineering field or equivalent practical experience.
Experience with C/C++ or RTL.
Academic coursework in computer architecture (core, cache, memory, etc)
MS or PhD degree in Computer Science, Electrical Engineering or related field.
Experience of designing/implementing or validating RTL design (core, cache, fabric, memory, codec, etc).
Knowledge of performance or power modeling of processor or ASIC architecture. Knowledge of performance or power architecture, power estimation, modeling, or optimization of processor or ASIC.
Knowledge of OS, Firmware, or software stack.
Proficient in a scripting language, C/C++ programming and software design skills
Perform performance validation and simulation using C/C++ and RTL-based models, and post-silicon performance correlation.
Perform analysis results in both qualitative and quantitative fashion effectively.
Create tools/scripts to automate test suites and models to improve functionality of simulators.
Participate in evaluation of future ASIC designs and general architecture.
Looking for Any Graduate graduates profile.