Job Description: Developing Physical design runsets for our process technologies is the primary job function. Working closely with the technology development teams in LTD (Logic Technology Division) to define and implement the technology rule documents and converting those process rules into physical verification runsets is the core function. Managing the stakeholders in TD group, flows and methods group in PESG and design team customers is the expanded functional role. Development of these runsets is on various EDA platform like SNPS (ICV), CDNS (PVS), Mentor (Calibre). Continuous improvement and ensuring the consistency of the results among these platforms is the day-to-day functions. Developing the specs for newer process nodes like 5nm, 3nm Intel technology will be forward looking challenge.Qualifications:BS or MS in Electrical/Electronics engineering. 12-15 years of experience is required in the physical design/ verification is required. Strong experience in developing the physical rule runsets in ICV/Calibre is very much required, with 8-10 years of experience in submicron technologies. Exposure to multi foundry technologies from TSMC, Samsung, Global and other competing foundries is very much desired. Strong management experience in managing the developers, QA engineers and other stakeholders is expected. Intel technology exposure from the past experience will be a real plus.
12-15 Years Of Experience Is Required In The Physical Design/ Verification Is Required. Strong Experience In Developing The Physical Rule Runsets In Icv/calib
Looking for Any Graduate / Post Graduate graduates profile.