Job DescriptionSuccessful candidate should be responsible for frontend chip design,synthesis,STA,formality flow Experience on 40nm or lower technologies Must have one or more complex silicon tapeout experience candidate should be able to work closely with design,verification and physical design team for resolving issues participate in SOC development planning and scheduling Job responsibilities are: 1.
participate in a global team setting on the development of PCIe,ethernet,USB3 domain 40nm chip design 2 Support design and verification of PCIE/Ethernet/USB3 products 3 Perform RTL design and verification of complex digital macros, working from an architectural description.
4 ASIC and FPGA Design flow through backend verification and streamout 5 Debug of complex silicon issues down to transistor level 6.
Technical Mentoring and supervision of Junior peopleJob RequirementsThe candidate must have BE (Electrical/Electronics) degree M.
E / M Tech (Electronics/Microelectronics) preferred Candidate should have worked on PCIe/Ethernet/USB3 domain Candidate must have 8 to 15 years of experience working in CMOS VLSI development capacity, preferably on products that incorporate PCIE/Ethernet/USB2/USB3 and microcontrollers for embedded control applications Strong digital design skills and experience in verilog/system RTL coding for synthesis is essential.
Experience with Synopsys tools (Linting,Design Compiler, IC Compiler, Power Compiler, Primetime) and formal verification tools is highly desirable The candidate will be working as a part of global VLSI design team Strong communication skill & the ability to interface effectively with US team members is essential Good scripting skills (Makefile/TCL/Perl)